One prior art flash memory device is a stack gate flash EEPROM where a single stack-gate transistor constitutes the memory cell. It programs as a traditional UV-erasable EPROM, using the mechanism of hot-electron injection to a floating gate, and erases through Fowler-Nordheim tunneling mechanism from the floating gate to the source region. Such device suffers the disadvantages of (1) over-erase sensitivity, where the memory cell can be erased to a negative threshold voltage thus rendering the cell in a conductive state even when the gate of the cell is deselected and biased at a ground potential, and (2) high programming current, which requires the memory cell to be programmed by a separate power supply voltage. See for example, U.S. Pat. No. 4,698,787.
A second type of flash memory device utilizes a split gate configuration. This eliminates the over-erase sensitivity, because even if the floating gate is over-erased, conduction in the channel requires the biasing of the control gate which is over another portion of the channel. However, the programming and erase mechanisms are the same as the stack-gate configuration. The disadvantage of this configuration is that it increases the cell size and can suffer an alignment sensitivity because of the split gate arrangement. See for example, U.S. Pat. No. 5,029,130.
Yet another type of flash memory cell utilizes the so called source-side injection technique which minimizes the hot electron programming current to the extent that an on-chip voltage multiplier can be used to provide sufficient programming current from a single 5 or 3.3 V power supply. However, the structure of these cells can still suffer from (1) alignment sensitivity, (2) poor scalability and (3) compromise between cell size and coupling ratio. See for example U.S. Pat. No. 5,194,925.
U.S. Pat. Nos. 5,303,187, 4,462,090 and 5,280,446 disclose a single transistor memory cell having four terminals with a select gate, a control gate, a source and a drain. The memory cell disclosed in U.S. Pat. No. 5,303,187, however, erases by tunneling of electrons from a floating gate to the substrate (see Col. 5, line 64-68). This is undesirable because of the lower coupling ratio, due to the large capacitance between the floating gate and the substrate. As a result, a higher voltage to erase is required. In addition, it requires a negative voltage to supply the potential for erase operation of an n-type cell. This requires the process to provide a high PMOS junction breakdown voltage, and a high field isolation threshold voltage and a low PMOS transistor body effect so that the circuit can provide a negative voltage of sufficient magnitude to achieve the necessary erase operation.
Each of U.S. Pat. Nos. 4,462,090 and 5,280,446 discloses a split gate configuration for the select gate. Such a split gate configuration for the select gate can cause punch through sensitivity due to misalignment.
U.S. Pat. No. 5,338,952 discloses a split gate memory cell with a floating gate formed as a spacer that is disposed adjacent the select gate and underneath the control gate. With this configuration, however, there is an insufficient amount of capacitive coupling between the floating gate and the control gate.
Lastly, the forgoing designs can suffer either avalanche or band-to-band breakdown during the erase operation where the source junction is biased to a relatively high potential. The breakdown voltage critically depends on the junction curvature as well as the oxide thickness at the edge of the junction. As cells are scaled down in size, the extent of curvature optimization is limited because of the reduced thermal cycles in the scaled technology.